A reverse conducting gate commutated thyristor (RC-GCT) combines one or more gate commutated thyristors (GCTs) and one or more diodes within a single power semiconductor device. A bi-mode gate commutated thyristor (BGCT) is a RC-GCT which includes, in a single semiconductor wafer, a plurality of GCT regions or cells electrically connected in parallel to one another, and a plurality of diode cells distributed between the GCT cells. The diode cells are also electrically connected in parallel to one another and to the GCT cells, albeit with opposing forward direction.
The diode cells provided in the semiconductor wafer allow for operating the BGCT in a diode mode, thus providing for reverse conductivity of the BGCT, which is required for a plurality of applications in power electronics.
A known BGCT is described in WO 2012/041958 A2, which is hereby included by reference in its entirety. FIG. 1 shows a cross-sectional view of the BGCT known from WO 2012/041958 A2.
The known BGCT 1′ includes a semiconductor wafer having a first main side 11 and a second main side 15. The second main side 15 is arranged parallel to the first main side 11. The known BGCT 1′ includes an (n−)-doped drift layer 3 located between—and extending in a direction parallel to—the first main side 11 and the second main side 15. The known BGCT 1′ also includes a plurality of GCT cells 91, where each GCT cell 91 includes layers in the wafer in the following order between the first main side 11 and the second main side 15: an n-doped thyristor cathode layer 4, a p-doped thyristor base layer 6, a thyristor drift layer 3′ (which is part of the drift layer 3), an n-doped thyristor buffer layer 8 and a (p+)-doped thyristor anode layer 5. The GCT cell 91 also includes a thyristor cathode electrode 2 arranged on the first main side 11 on each thyristor cathode layer 4, a thyristor anode electrode 25 arranged on the second main side 15 on each thyristor anode layer 5, and a plurality of gate electrodes 7 arranged on each thyristor base layer 6 lateral to, but separated from, the thyristor cathode electrode 2 and the thyristor cathode layer 4. The gate electrodes 7 contact the p-doped thyristor base layer 6.
In addition, the BGCT 1′ includes a plurality of diode cells 96 which include layers in the following order in the semiconductor wafer between the first and second main sides 11, 15: a p-doped diode anode layer 55, a diode drift layer 3″ (which is part of the drift layer 3), and an n-doped diode cathode layer 45, which is arranged alternating to the thyristor anode layer 5 adjacent to the second main side 15. Finally, the BGCT 1′ includes a diode anode electrode 28 arranged on the first main side 11 on each diode anode layer 55. The plurality of diode cells 96 form the diode part of the reverse conducting semiconductor device of the BGCT 1′.
The diode cells 96 are separated from the GCT cells 91 by uniform separation regions 350, which are formed by parts of the drift layer 3 located between the diode cells 96 and GCT cells 91 and where the drift layer 3 extends to the first main side 11.
For a known BGCT, in the GCT mode operation, the dedicated diode regions are utilized during conduction due to the plasma (charge) spreading into those regions. In the diode mode operation, the dedicated GCT regions are also utilized. The tilted arrows in FIG. 1 show the expected plasma spread in GCT mode operation, which can be inverted for the diode mode.
The dimensioning of the GCT cells 91 and separation area between the diode and GCT cells 91, 96 is an important factor for area utilization. The separation regions 350 must be designed to enable the required blocking capability for the gate drive (gate cathode blocking capability, e.g., −20 V during GCT turn off and blocking) while keeping the dimensions (separation region distance) to a minimum for total area utilization (in order to enable plasma spreading from GCT regions 91 to dedicated diode regions 96 in the GCT mode of operation and vice versa).
In high voltage devices like BGCTs 1′, the N−-base (N-drift layer) is usually very low doped and if the separation region distance is small, there is a possibility for the punch-through effect and eventually this region cannot block the required gate drive voltage. Even if the small separation distance is enough to block the required gate drive voltage (during turn-off and blocking), there will be a high gate cathode leakage current since PNP (p-thyristor base layer 6, n-drift layer 3, p-diode anode layer 55) gain is too high due to the low doped n-drift layer 3 and a small distance of the n-drift layer 3 between the thyristor base layer 6 and the diode anode layer 55, i.e., the width of the separation region 350.